||-||Not implemented, Read as 0.|
||EEIF||1: Write is complete (must be cleared by software).
0: The write operation is not complete or has not been started.
||WRERR||1:A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation).
0:The write operation completed.
||WREN||1:Allows write cycles.
0:Inhibits write to the EEPROM.
||WR||1:Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0:Write cycle to the EEPROM is complete.
||RD||1:Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0:Does not initiate an EEPROM read